Featured image of post My Talk About Silicon Chips Reverse Engineering and Degate
Hardware Talk

My Talk About Silicon Chips Reverse Engineering and Degate

Introduce a talk about silicon chips RE and Degate I presented at multiple conferences in 2024.

NEW

Talk PDF and sources are available here, and are under CC0 (Public Domain) license.

My work on silicon chips reverse engineering or Degate is a hobby, and doesn’t constitute my main area of expertise, and is not related to what I do professionally (mostly malware development/analysis). Everything here was done in my spare time.

Introduction

In 2024, I participated in multiple conferences/events to present the silicon chips reverse engineering domain, and more precisely Degate. This post depicts this journey.

gantt
    title Talk's Journey
    dateFormat YYYY-MM-DD
    todayMarker off
    tickInterval 2month

    Talk Creation: a1, 2024-02-15, 2024-05-08
    Bière Sécu Rennes 2: milestone, crit, m1, 2024-05-14, 0d
    FSiC2024: milestone, crit, m2, 2024-06-20, 0d
    HTB Meetup Rennes: milestone, crit, m3, 2024-09-05, 0d
    SecSea2k24: milestone, crit, m4, 2024-10-12, 0d

To give some context on the talk, a small introduction around silicon chips reverse engineering and Degate is available below.

Silicon Chips Reverse Engineering

To assess the security of a product or software, you can use a wide range of procedures, even under Black Box conditions. For example, you can use software reverse engineering to audit a proprietary firmware, perform dynamic analysis on an undocumented binary or analyze output traffic. However, when it comes to hardware implementations, things can get complicated. What can we do against a cryptographic algorithm that may be weak, but totally undocumented, and that is implemented directly into the silicon, using transistors and logic gates? Fortunately, there are some techniques available to tackle this specific issue and retrieve information about a hardware implementation, such as side-channel attacks or silicon chips reverse engineering (not exhaustive).

Side channel attacks are quite widely explored, but silicon chips reverse engineering isn’t. Here the idea is to retrieve an algorithm implemented directly into the silicon, using transistors, from only a chip as base material. The process is analogous to software reverse engineering, where you start from a binary, and then retrieve assembly and then code. But here, we’ll start with a silicon chip, get images, then identify transistors, logic gates, retrieve the netlist and then the underlying algorithm. Simplifying, we can see side channel attacks as dynamic analysis, and silicon chips reverse engineering as static analysis. Chips reverse engineering can be used in many different use cases, from old hardware analysis to build software emulators to intellectual property check, passing by vulnerabilities and backdoors identification. It can also be used by foundries to perform fault and failure detection, but they are not working at the same scale.

Silicon chips reverse engineering can be cut into five main steps:

  1. Chip capture using decapsulation, delayering, stitching and more.
  2. Transistor and gate identification.
  3. Wires and vias analysis, connecting all the identified gates.
  4. Netlist generation, allowing simulation and error spotting.
  5. Algorithm retrieval with an additional analysis step, when the netlist is too big or too complex to be exploited directly.

The image below is summarizing that process:

Silicon Chips Reverse Engineering process

To perform that process, we first need to capture the chip, this passes by decapsulation, the selection of an area of interest, delayering, cleaning and stitching. Then, we have to analyze each specific gate layout to build our gate library, starting with transistors. Using pattern matching, we can then use that library to retrieve all other gate instances. After that, we need to trace the wires and vias to connect together all the identified gates, inputs and outputs. Which will give us, after having described each gate in an HDL language, the full netlist. We can simulate that netlist to start spotting errors in the analysis. And, if the netlist is huge, we can use automated processes and methods to extract the underlying algorithm, discover specification and build a software emulator.

The below image present an example of a logic gate analysis:

Example analysis of some transistors forming a logic gate

Analyzing transistors is the base task of silicon chips reverse engineering, and is mostly manual work, even if it can be automated for some capture method using auto-vectorization. At first glance it can be seen as a hard process to master, but in the end transistor identification is easy with practice. In reality, the hardest challenge is wires and vias identification, which impose at least semi-automation since there is so much wires on a chip. Any mistake is very difficult to spot, and can impact the whole resulting netlist. And if you add obfuscation, like creating false wires or vias, the analysis can become a nightmare.

If you are interested in a deeper explanation/presentation of silicon chips reverse engineering, please refer to the talk materials. I also may post a full blog post on the subject, if there is interest.

Degate

As described before, silicon chips reverse engineering is a complex process that can take months. Therefore automation is the key, and here come Degate, a multi-platform and open source software for semi-automatic VLSI chips reverse engineering. It offers a GUI and help on multiple steps of the process of reversing a silicon chip. It’s a medium-sized software with fewer than one hundred thousand lines of codes. It supports the three major OSes and is Qt based. Translations are available for multiple language to ease the adoption. It offers many features like gate definition, gate, via and wire matching or electrical rule checks for error spotting.

Degate help to reverse VLSI chips by creating a gate library from your analysis, provides algorithms for template matching used for finding gate instances, can perform wires and vias matching, allows exporting netlist or can simply help navigate really huge images. Here the focus is on modern ICs with standard cells, and Degate support any 2D capture or imaging method. Hence, contrary to many commercial products, we don’t force any specific capture method and try to support as many possible.

Overview of Degate software

Degate is not a new software, it has already quite a long history. Therefore, it also comes with some technical debt since we tried to follow major IC evolution, like in transistor size and count. Degate was first started by Martin Schobert during his master’s thesis, in 2007, with some famous hardware cipher analysis performed using the software. But, at the end of Martin’s thesis in 2010, a minimum maintenance period occurred. No major feature was added, and the field was quite silent. I forked the initial version of Degate in 2018 and did a major rewrite, with a near 70% code rewritten from scratch.

The current version of Degate focus on gate library system, automatic gate instances identification, and wires & vias recognition. We also fully provide netlist generation in multiple formats. However we don’t currently support transistors and gate analysis or automatic identification, and don’t help on netlist analysis. In the next major release of Degate we plan to extend that coverage.

Scope of Degate software

Since 2018, I’m the official maintainer of Degate, and lead the development of the software.

Conferences

I had the chance to be contacted by the Free Silicon Foundation at the start of 2024 to perform a talk on Degate at FSiC 2024. With such opportunity, I created a support from scratch presenting silicon chips reverse engineering and Degate. I then started to perform this talk to different events and conferences, starting in May 2024 until October 2024.

The following sections present those events and conferences. Also please note that the full presentation deck is too large to fully be presented during each talk, so each time I make a presentation on the subject, the support differ a bit.

Local events

I participated in two local events, in Rennes, namely “Bière Sécu’ Rennes” (in May) and “Hack the Box Meetup” (in September). These smaller events are interesting to battle-test new talks, but are also full of profiles we don’t generally see at other bigger conferences (in my opinion). This allowed many great discussions about Degate, that even were the most technical ones.

Before going to those events, and particularly to the first (Bière Sécu’ Rennes), I wasn’t very confident that the subject could interest anyone, since it is very technical and touch very uncommon subjects. However, I had very positive feedback from people of very different backgrounds. The introduction of the silicon chips reverse engineering field seemed to have been very appreciated, to my surprise.

BSR2 in Rennes, May 2024

As a side note, I will try to present a new talk in these local events soon (should be on malware development).

Free Silicon Conference 2024

I had the chance to be invited by the Free Silicon Foundation to give a talk in June 2024, which allowed me to discover their implication for more open chips/SoC. The F-Si Foundation is a nonprofit organization which promote Free and Open Source (FOS) Computer-Aided Design (CAD) tools/software (for integrated circuits design), hardware designs and libraries, common standards and freedom of users. Since 2019 (with a pause due to the pandemic), they organize the Free Silicon Conference at La Sorbonne in Paris. This is an international event, hence all talks are performed in English. It offers a nice mix of academic and professional people, creating nice synergy and deep technical discussions.

This was in fact my first (ever) conference (opposed to smaller local events), as a speaker and as a participant. The public was also not very cybersecurity oriented, and mainly focused on low (and very low) level hardware design. So it wasn’t an easy journey, and was quite stressful (which impacted my English during the talk).

This was the official abstract of the talk:

In recent years, there has been a growing emphasis on security and trust in software and infrastructure, where security through obscurity is increasingly being countered by numerous auditing and reverse-engineering tools. In a context where many safety-critical components are implemented in hardware (TPM, cryptography, biometric authentication, crypto-asset securitization, RFID…), we cannot trust a system simply by checking and validating its software (firmware, driver…). While analyzing PCBs is accessible, going into the silicon to check implementations’ security is a lot more complex and costly, but remain one of the only solution to fully trust a closed system (let aside reimplementation).

Degate is an open-source tool for reverse engineering silicon chips, aimed at providing a complete workflow (from chip images to VHDL/Verilog) for community-led analysis. It can be used to understand old and recent chips, to check algorithms’ implementations or to search for vulnerabilities and backdoors.

This talk introduces Degate, presents the challenges of reverse engineering silicon chips and shows a real-world analysis that led to critical discoveries. We first present the importance of low-level hardware validation for security, and list the tools and products available for this task. We then outline the background and current status of Degate, and all the associated engineering and research challenges. Finally, we take the famous case of the MIFARE Classic RFID chip as an example and look at the future horizon of reverse engineering silicon chips.

To be honest, regarding the areas of expertise of the public, I wasn’t sure if my talk could interest peoples (again), but in the end I got very nice feedback (again). The silicon chips reverse engineering field is so unknown, and connect so many specialties, that it actually has a fairly large potential audience. I also had interesting interactions after the talk, which confirmed the attractiveness of the field.

FSiC 2024 in La Sorbonne, June 2024

SecSea2k24

Then, in October, I had the chance to make the closing talk of the SecSea 2024 conference. It was organized by the Hack In Provence association for its sixth edition, in the oldest cinema in the world, the Eden Cinema in La Ciotat. For me, it’s a very special event since no sponsor is authorized, and everything is oriented towards the community. This allows very different subjects and approaches to be presented, and is very welcoming to new speaker. In the end, it was the perfect place to present the silicon chips reverse engineering field, even if the public was very focused on the cybersecurity domain, with only a few people with bases in electronics or physics. This might be the best experience of the year I had presenting this talk.

Once again, I got interesting feedback about my presentation, and had the chance to have a talk on a side-channel attack at the opening of the conference, allowing the audience to have a panoramic view of the domain. And, at my surprise, I got cited on multiple posts regarding the conference afterward, with some people describing the talk as “intellectually challenging but enriching”.

SecSea2k24, La Ciotat, October 2024

This final event concluded the presentation window for this talk, although I may present it again at other venues if there is interest.

Resources

You can find all the presentation supports of each talk on my website, the “final” version here and the sources on my github.

   Presentation PDF
Download

  Presentation Sources
Source

   1
   2
   3
   4
   5
   6
   7
   8
   9
  10
  11
  12
  13
  14
  15
  16
  17
  18
  19
  20
  21
  22
  23
  24
  25
  26
  27
  28
  29
  30
  31
  32
  33
  34
  35
  36
  37
  38
  39
  40
  41
  42
  43
  44
  45
  46
  47
  48
  49
  50
  51
  52
  53
  54
  55
  56
  57
  58
  59
  60
  61
  62
  63
  64
  65
  66
  67
  68
  69
  70
  71
  72
  73
  74
  75
  76
  77
  78
  79
  80
  81
  82
  83
  84
  85
  86
  87
  88
  89
  90
  91
  92
  93
  94
  95
  96
  97
  98
  99
 100
 101
 102
 103
 104
 105
 106
 107
 108
 109
 110
 111
 112
 113
 114
 115
 116
 117
 118
 119
 120
 121
 122
 123
 124
 125
 126
 127
 128
 129
 130
 131
 132
 133
 134
 135
 136
 137
 138
 139
 140
 141
 142
 143
 144
 145
 146
 147
 148
 149
 150
 151
 152
 153
 154
 155
 156
 157
 158
 159
 160
 161
 162
 163
 164
 165
 166
 167
 168
 169
 170
 171
 172
 173
 174
 175
 176
 177
 178
 179
 180
 181
 182
 183
 184
 185
 186
 187
 188
 189
 190
 191
 192
 193
 194
 195
 196
 197
 198
 199
 200
 201
 202
 203
 204
 205
 206
 207
 208
 209
 210
 211
 212
 213
 214
 215
 216
 217
 218
 219
 220
 221
 222
 223
 224
 225
 226
 227
 228
 229
 230
 231
 232
 233
 234
 235
 236
 237
 238
 239
 240
 241
 242
 243
 244
 245
 246
 247
 248
 249
 250
 251
 252
 253
 254
 255
 256
 257
 258
 259
 260
 261
 262
 263
 264
 265
 266
 267
 268
 269
 270
 271
 272
 273
 274
 275
 276
 277
 278
 279
 280
 281
 282
 283
 284
 285
 286
 287
 288
 289
 290
 291
 292
 293
 294
 295
 296
 297
 298
 299
 300
 301
 302
 303
 304
 305
 306
 307
 308
 309
 310
 311
 312
 313
 314
 315
 316
 317
 318
 319
 320
 321
 322
 323
 324
 325
 326
 327
 328
 329
 330
 331
 332
 333
 334
 335
 336
 337
 338
 339
 340
 341
 342
 343
 344
 345
 346
 347
 348
 349
 350
 351
 352
 353
 354
 355
 356
 357
 358
 359
 360
 361
 362
 363
 364
 365
 366
 367
 368
 369
 370
 371
 372
 373
 374
 375
 376
 377
 378
 379
 380
 381
 382
 383
 384
 385
 386
 387
 388
 389
 390
 391
 392
 393
 394
 395
 396
 397
 398
 399
 400
 401
 402
 403
 404
 405
 406
 407
 408
 409
 410
 411
 412
 413
 414
 415
 416
 417
 418
 419
 420
 421
 422
 423
 424
 425
 426
 427
 428
 429
 430
 431
 432
 433
 434
 435
 436
 437
 438
 439
 440
 441
 442
 443
 444
 445
 446
 447
 448
 449
 450
 451
 452
 453
 454
 455
 456
 457
 458
 459
 460
 461
 462
 463
 464
 465
 466
 467
 468
 469
 470
 471
 472
 473
 474
 475
 476
 477
 478
 479
 480
 481
 482
 483
 484
 485
 486
 487
 488
 489
 490
 491
 492
 493
 494
 495
 496
 497
 498
 499
 500
 501
 502
 503
 504
 505
 506
 507
 508
 509
 510
 511
 512
 513
 514
 515
 516
 517
 518
 519
 520
 521
 522
 523
 524
 525
 526
 527
 528
 529
 530
 531
 532
 533
 534
 535
 536
 537
 538
 539
 540
 541
 542
 543
 544
 545
 546
 547
 548
 549
 550
 551
 552
 553
 554
 555
 556
 557
 558
 559
 560
 561
 562
 563
 564
 565
 566
 567
 568
 569
 570
 571
 572
 573
 574
 575
 576
 577
 578
 579
 580
 581
 582
 583
 584
 585
 586
 587
 588
 589
 590
 591
 592
 593
 594
 595
 596
 597
 598
 599
 600
 601
 602
 603
 604
 605
 606
 607
 608
 609
 610
 611
 612
 613
 614
 615
 616
 617
 618
 619
 620
 621
 622
 623
 624
 625
 626
 627
 628
 629
 630
 631
 632
 633
 634
 635
 636
 637
 638
 639
 640
 641
 642
 643
 644
 645
 646
 647
 648
 649
 650
 651
 652
 653
 654
 655
 656
 657
 658
 659
 660
 661
 662
 663
 664
 665
 666
 667
 668
 669
 670
 671
 672
 673
 674
 675
 676
 677
 678
 679
 680
 681
 682
 683
 684
 685
 686
 687
 688
 689
 690
 691
 692
 693
 694
 695
 696
 697
 698
 699
 700
 701
 702
 703
 704
 705
 706
 707
 708
 709
 710
 711
 712
 713
 714
 715
 716
 717
 718
 719
 720
 721
 722
 723
 724
 725
 726
 727
 728
 729
 730
 731
 732
 733
 734
 735
 736
 737
 738
 739
 740
 741
 742
 743
 744
 745
 746
 747
 748
 749
 750
 751
 752
 753
 754
 755
 756
 757
 758
 759
 760
 761
 762
 763
 764
 765
 766
 767
 768
 769
 770
 771
 772
 773
 774
 775
 776
 777
 778
 779
 780
 781
 782
 783
 784
 785
 786
 787
 788
 789
 790
 791
 792
 793
 794
 795
 796
 797
 798
 799
 800
 801
 802
 803
 804
 805
 806
 807
 808
 809
 810
 811
 812
 813
 814
 815
 816
 817
 818
 819
 820
 821
 822
 823
 824
 825
 826
 827
 828
 829
 830
 831
 832
 833
 834
 835
 836
 837
 838
 839
 840
 841
 842
 843
 844
 845
 846
 847
 848
 849
 850
 851
 852
 853
 854
 855
 856
 857
 858
 859
 860
 861
 862
 863
 864
 865
 866
 867
 868
 869
 870
 871
 872
 873
 874
 875
 876
 877
 878
 879
 880
 881
 882
 883
 884
 885
 886
 887
 888
 889
 890
 891
 892
 893
 894
 895
 896
 897
 898
 899
 900
 901
 902
 903
 904
 905
 906
 907
 908
 909
 910
 911
 912
 913
 914
 915
 916
 917
 918
 919
 920
 921
 922
 923
 924
 925
 926
 927
 928
 929
 930
 931
 932
 933
 934
 935
 936
 937
 938
 939
 940
 941
 942
 943
 944
 945
 946
 947
 948
 949
 950
 951
 952
 953
 954
 955
 956
 957
 958
 959
 960
 961
 962
 963
 964
 965
 966
 967
 968
 969
 970
 971
 972
 973
 974
 975
 976
 977
 978
 979
 980
 981
 982
 983
 984
 985
 986
 987
 988
 989
 990
 991
 992
 993
 994
 995
 996
 997
 998
 999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105

\documentclass[aspectratio=169]{beamer}
\usetheme{AnnArbor}

\definecolor{degatered}{rgb}{0.902,0.22,0.161}
\setbeamercolor{titlelike}{parent=structure,fg=white,bg=degatered}
\setbeamercolor*{palette primary}{bg=degatered!50!black,fg=white}
\setbeamercolor*{palette secondary}{bg=degatered!40!black,fg=white}
\setbeamercolor*{palette tertiary}{bg=degatered!30!black,fg=white}
\setbeamercolor*{palette quaternary}{bg=degatered!20!black,fg=white}
\setbeamercolor{frametitle}{bg=degatered}
\setbeamercolor{frametitle right}{bg=degatered!60!black}
\setbeamertemplate{bibliography item}{\insertbiblabel}

\usepackage{tikz}

\title{\textbf{\underline{Degate}}}
\subtitle{The stakes and challenges of silicon reverse engineering \\ \url{https://www.degate.org}}
\titlegraphic{\includegraphics[width=2cm]{res/degate.png}}
\author{\textbf{D.~Bachelot}}
\date{\textbf{\underline{Degate Community}},\\ 2024}
\logo{\includegraphics[scale=0.08]{res/degate.png}}

\AtBeginSection[ ]
{
	\begin{frame}{}
		\tableofcontents[currentsection]
	\end{frame}
}

\begin{document}
	
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}[plain]
    \maketitle
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\begin{frame}{}
	\tableofcontents
\end{frame}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\section{Silicon Chips Reverse Engineering}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

	\subsection{Introduction}
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	\begin{frame}{}
		\tableofcontents[currentsection, currentsubsection]
	\end{frame}
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{What is Silicon Chips RE?}
		\begin{tabular}{cl}  
			
			\begin{tabular}{c}
				\includegraphics[width=5.2cm]{res/chip_example.png}
			\end{tabular}
			
			& \begin{tabular}{l}
				\parbox{0.5\linewidth}{\scriptsize
					Same idea than with software RE (from binary, to assembly and to code), silicon chip RE go \textbf{from silicon}, \textbf{to images}, \textbf{to transistors}, \textbf{to gates}, \textbf{to netlist} and \textbf{to algorithm}. \\
		
					With proper preparation and knowledge, we can go into silicon, \textbf{analyze transistors}, \textbf{retrieve gates/wires/vias} and \textbf{reconstruct implemented algorithms}. This can be used to \textbf{analyze old hardware}, build \textbf{software emulators}, search for \textbf{vulnerabilities} and \textbf{backdoors}, \textbf{break/test a protection}, \textbf{secret extraction} or \textbf{check intellectual property}. \\
					
					\textbf{Used in IC industry} for \textbf{fault/failure detection} \& analysis, but \textbf{not at the same scale}.
				}
			\end{tabular}
		
		\end{tabular}
		
		\begin{figure}[!ht]
			\centering
			\resizebox{0.7\textwidth}{!}{%
				\begin{tikzpicture}
					\tikzstyle{every node}=[font=\normalsize]
					\draw  (10.5,17.75) circle (2.5cm) node [text width=4cm]
					{ \Large
						\centering \textbf{Image chip} \\
						\vspace{3mm}
						\textit{(or SEM scan or 3D tomography)}
					} ;
					\draw  (16.5,17.75) circle (2.5cm) node {\Large \textbf{Analyze Gates}} ;
					\draw  (22.5,17.75) circle (2.5cm) node {\Large \textbf{Trace Wires/Vias}} ;
					\draw  (28.5,17.75) circle (2.5cm) node {\Large \textbf{Generate Netlist}} ;
					\draw [, dashed] (34.5,17.75) circle (2.5cm) node {\Large \textbf{Retrieve Algorithm}} ;
					\draw [->] (13,17.75) -- (14,17.75);
					\draw [->] (19,17.75) -- (20,17.75);
					\draw [->] (25,17.75) -- (26,17.75);
					\draw [->] (31,17.75) -- (32,17.75);
				\end{tikzpicture}
			}%
		\end{figure}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{How to Access Silicon?}	
		Can be very costly (plasma \& laser) and destructive... But also accessible with simpler methods (like chemical/mechanical). More on \cite{SiliconPron}.
		
		\begin{enumerate}
			\item \textbf{Decapsulation} (heat, acid, mechanical, plasma, laser...)
			\item \textbf{Delayering} (chemical, abrasive, laser, plasma...)
			\item \textbf{Cleaning} (ultrasound, acid...)
		\end{enumerate}
		
		\begin{center}
			\includegraphics[width=4cm]{res/decap.jpg}
			\cite{Holler2017}
			\includegraphics[width=3cm]{res/delayer.png}
			\cite{KarstenNohl2009}
			\includegraphics[width=4.5cm]{res/delayered.png}
			\tiny MIT
		\end{center}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{How to Retrieve Images?}
		Using each layer (invasive) or directly using the chip (non-invasive):
		\begin{itemize}
			\item Take very-high resolution images from \textbf{optical microscope} (basic, confocal) ;
			\item Scan from an \textbf{electron microscope} (SEM, TEM...) ;
			\item Generate a 3D model using \textbf{electron tomography} ;
		\end{itemize}
		
		\begin{center}
			\includegraphics[width=5cm]{res/3d_1.png}
			\includegraphics[width=5.4cm]{res/3d_2.png}
			\cite{Holler2017}
		\end{center}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{How to Perform the Analysis?}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{c}
				\parbox{0.5\linewidth}{
					\vspace{-3mm}
					Overview:
					\begin{enumerate}
						\item Choose a \textbf{zone of interest},
						\item Identify each \textbf{gate type}, annotate, and place in a \textbf{"gate library"},
						\item Find other \textbf{gates instance} from gate library,
						\item Link gates by tracing \textbf{wires and vias},
						\item Export to \textbf{netlist} (e.g. by translating each gate to VHDL/Verilog code).
					\end{enumerate}
				}
			\end{tabular}
			
			& \begin{tabular}{l}
				\includegraphics[width=6.25cm]{res/transistor.png}
			\end{tabular}
			
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{How to identify a transistor?}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{c}
				\parbox{0.5\linewidth}{\small
					\begin{enumerate}
						\item Search, at transistor layer, for \textbf{doped zones}.
						\item Spot the \textbf{zebras}.
						\item Use logic to identify the \textbf{type of each transistor} (e.g. PMOS are bigger to compensate with lower hole mobility).
						\item Search for \textbf{wires} (to identify inputs and outputs).
					\end{enumerate}
				}
			\end{tabular}
			
			& \begin{tabular}{l}
				\includegraphics[width=4cm]{res/npn.png}
				\vspace{10mm} 
				\tiny (NMOS, \textit{Wikipedia})
			\end{tabular}
			
		\end{tabular}
		
		\centering
		\hspace{-40mm}
		\includegraphics[width=2.5cm]{res/cmos.png}
		\tiny (Inverter, \textit{Wikipedia})
		\hspace{6mm}
		\includegraphics[width=3cm]{res/dopant_pmos.png}
		\tiny (PMOS \cite{YenerBulent2014})
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{How to Identify a Gate?}
		
		\begin{tabular}{ccc}  
			\begin{tabular}{c}  
				
				\begin{tabular}{ccc}
					\includegraphics[width=1.75cm]{res/ana_1.png} &
					\includegraphics[width=1.75cm]{res/ana_2.png} &
					\includegraphics[width=1.75cm]{res/ana_3.png} \\
					\tiny Transistor layer &
					\tiny Logic layer &
					\tiny Metal layer \\
				\end{tabular} \\
				
				$\Downarrow$ \\
				
				\begin{tabular}{cc}
					\tiny
					\includegraphics[width=1.75cm]{res/post_ana_1.png} &
					\includegraphics[width=1.75cm]{res/post_ana_2.png} \\
					\tiny P \& N zones and 2 inputs &
					\tiny V+ \& V-, and output \\
				\end{tabular}
				
			\end{tabular} &
			
			$\Rightarrow$
			
			& 
			
			\ensuremath{\vcenter{\hbox{\includegraphics[width=3cm]{res/ana_layout.png}}}}
			{\tiny\cite{SiliconZoo}}
			$\Rightarrow$
			\begin{tabular}{c}
				\textbf{NAND gate!} \\
				\includegraphics[width=2.5cm]{res/nand.png} \\
				\begin{tabular}{ | c | c || c | }
					\hline
					A & B & Y \\
					\hline
					0 & 0 & 1 \\
					1 & 0 & 1 \\
					0 & 1 & 1 \\
					1 & 1 & 0 \\
					\hline
				\end{tabular}
			\end{tabular} \\
			
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{How to Retrieve the Netlist from Analyzed Gates?}
		\begin{tabular}{cl}  
			
			\begin{tabular}{c}
				\includegraphics[width=6cm]{res/verilog.png}
			\end{tabular}
			
			& \begin{tabular}{l}
				\parbox{0.5\linewidth}{\scriptsize
					\begin{itemize}
						\item Each gate can be described with \textbf{hardware description language (HDL)}, like \textbf{Verilog} or \textbf{VHDL}.
						\item \textbf{Wires \& vias} can also be described.
						\item That's all we need to \textbf{obtain the netlist}!
					\end{itemize}
					
					We can, from HDL, \textbf{simulate the extracted netlist} and \textbf{find incoherence} (\textit{example with gtkwave below}):
					
					\vspace{2mm}
					
					\includegraphics[width=7cm]{res/gtkwave.png}
				}
			\end{tabular}
			
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{How to Get the Algorithm/Specification from Netlist? \cite{LeonidAzriel2021}}
		\small
		
		After retrieving the \textbf{netlist}, we are left with a \textbf{huge and "unorganized" number of gates}. The \textbf{specification discovery} phase aims to \textbf{retrieve IC's algorithm/functionality} from the extracted netlist.
		
		\vspace{3mm}
		
		Using specific algorithms you can \textbf{automate some phase}:
		\begin{itemize}
			\item \textbf{Partitioning} of the netlist (\textit{to retrieve a semblance of "code" structure}).
			\item \textbf{Recovery} of the registers (\textit{if applicable}).
			\item \textbf{Identification} of the extracted "groups" (\textit{partitions}) of the netlist.
			\item \textbf{Construction} of a library of netlist components from the identified "groups".
		\end{itemize}
		
		\vspace{3mm}
		
		These algorithms \textbf{need to allow some degrees of error} from the netlist extraction. This phase is $\sim$analogous with \textbf{duplicated, standard \& library functions identification} for \textbf{software engineering}. A nice open source tool for this is \textbf{HAL}\footnote{https://github.com/emsec/hal} (compatible with Degate's outputs!).
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{To Summarize}
		
		\begin{figure}[!ht]
			\centering
			\resizebox{0.8\textwidth}{!}{%
				\begin{tikzpicture}
					\tikzstyle{every node}=[font=\normalsize]
					\draw  (10.5,17.75) circle (2.5cm) node [text width=4cm]
					{ \Large
						\centering \textbf{Image chip} \\
						\vspace{3mm}
						\textit{(or SEM or 3D tomography)}
					} ;
					\draw  (16.5,17.75) circle (2.5cm) node {\Large \textbf{Analyze Gates}} ;
					\draw  (22.5,17.75) circle (2.5cm) node {\Large \textbf{Trace Wires/Vias}} ;
					\draw  (28.5,17.75) circle (2.5cm) node {\Large \textbf{Generate Netlist}} ;
					\draw [, dashed] (34.5,17.75) circle (2.5cm) node {\Large \textbf{Retrieve Algorithm}} ;
					\draw [->] (13,17.75) -- (14,17.75);
					\draw [->] (19,17.75) -- (20,17.75);
					\draw [->] (25,17.75) -- (26,17.75);
					\draw [->] (31,17.75) -- (32,17.75);
					
					\draw [, dashed] (8.25,15) rectangle  node [text width=4cm] 
					{ 
						- \textbf{Decapsulate}, \\
						- Select \textbf{area of interest}, \\
						- \textbf{Delayer}, \\
						- Clean, \\
						- Stitch.
					}  (12.75,10.25);
					
					\draw [, dashed] (14.25,15) rectangle  node [text width=4cm]
					{ 
						- Analyze transistors, \\
						- \textbf{Identify each type of gates}, \\
						- Retrieve all instances of each gate (\textbf{pattern matching}).
					}  (18.75,10.25);
					
					\draw [, dashed] (20.25,15) rectangle  node [text width=4cm]
					{
						- Identify \textbf{wires}, \\
						- Identify \textbf{vias}, \\
						- \textbf{Connect gates}.
					}  (24.75,10.25);
					
					\draw [, dashed] (26.25,15) rectangle  node [text width=4cm]
					{ 
						- \textbf{Export netlist}, \\
						- Gate simulation, \\
						- Try to identify errors.
					}  (30.75,10.25);
					
					\draw [, dashed] (32.25,15) rectangle  node [text width=4cm]
					{
						- Extract algorithm, \\
						- \textbf{Discover specification}, \\
						- Perform functional analysis\cite{LeonidAzriel2021}, \\
						- Build a \textbf{software emulator}, \\
						- Try to \textbf{identify errors}.
					}  (36.75,10.25);
					
					\draw [] (10.5,15.25) -- (10.5,15);
					\draw [] (16.5,15.25) -- (16.5,15);
					\draw [] (22.5,15.25) -- (22.5,15);
					\draw [] (28.5,15.25) -- (28.5,15);
					\draw [] (34.5,15.25) -- (34.5,15);
					

					\node (tikzmaker) [shift={(2.75, -0)}] at (7.5,7.25) {\includegraphics[width=5cm]{res/how_1.png}\cite{KarstenNohl2009}};
					\node (tikzmaker) [shift={(2.75, -0)}] at (13.5,7.25) {\includegraphics[width=5cm]{res/how_2.png}\cite{KarstenNohl2009}};
					\node (tikzmaker) [shift={(2.75, -0)}] at (19.5,6.5) {\includegraphics[width=5cm]{res/how_3.png}\cite{KarstenNohl2009}};
					\node (tikzmaker) [shift={(2.75, -0)}] at (25.5,7.25) {\includegraphics[width=5cm]{res/how_4.png}\cite{KarstenNohl2009}};
					\node (tikzmaker) [shift={(2.75, -0)}] at (31.75,7.25) {\includegraphics[width=5cm]{res/how_5.png}\cite{KarstenNohl2009}};
					
					\draw [, dashed] (10.25,10.25) -- (10.25,9.75);
					\draw [, dashed] (16.25,10.25) -- (16.25,9.75);
					\draw [, dashed] (22.25,10.25) -- (22.25,9.75);
					\draw [, dashed] (28.5,10.25) -- (28.5,9.75);
					\draw [, dashed] (34.5,10.25) -- (34.5,9.75);
				\end{tikzpicture}
			}%
		\end{figure}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

	\subsection{Challenges}
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	\begin{frame}{}
		\tableofcontents[currentsubsection]
	\end{frame}
		
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Cost Perspective (1/2)}
		\textbf{Costly solutions will give best results}, and sometime reduce the difficulty for analysis software:
		\begin{itemize}
			\item \textbf{Decapsulation/delayering:} plasma, laser, FIB ;
			\item \textbf{Imaging:} Scanning Electron Microscope (SEM), other electron microscope (TEM, STEM, LEEM, PEEM...) ;
			\item \textbf{3D modelization:} electron tomography (3D) ;
		\end{itemize}
		
		\vspace{3mm}
		
		Simpler methods rely on \textbf{mechanical \& chemical} decapsulation/delayering and \textbf{optical microscopes} to obtain \textbf{very-high resolution but imperfect images}. Using images is more challenging: \textbf{color channels}, \textbf{impurity/damage/dust}, \textbf{single dimension}, \textbf{stitching}, \textbf{resolution}, \textbf{laborious work}...
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Cost Perspective (2/2)}
		\textbf{Chip samples cost} are also to consider (when doing invasive analysis, you'll maybe need multiple samples of the chip).
		
		\vspace{3mm}
		
		Compared to software reverse engineering, there is a \textbf{lot more costs associated}, and a \textbf{higher entry barrier}.
		
		\vspace{3mm}
		
		\begin{tabular}{cl}  
		
			\begin{tabular}{c}
				\includegraphics[width=7.5cm]{res/sem.png}
			\end{tabular}
			
			& \begin{tabular}{l}
				\parbox{0.4\linewidth}{\small
					A \textbf{new SEM microscope} can cost from \textbf{70k\$ to over 1M\$}. \textbf{Used instruments} can cost from \textbf{2,5k\$ to 550k\$}. Resolution may vary a lot. \\
					
					And that's \textbf{just for imaging}!
					
					\vspace{12mm}
					
					\textit{(Umeå University)}
				}
			\end{tabular}
			
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Analysis Perspective}
		\begin{itemize}
			\item Newest chips \textbf{have $\sim$3nm transistors} and \textbf{billions of them}!
			\item Need automatic \textbf{gate recognition, wire tracing and netlist reconstruction}, which a human can't handle alone.
			\item Resulting images can be \textbf{millions of pixels large} ($width$ $>$ million pixels)!
			\item How to perform \textbf{template matching/image recognition} on such \textbf{gigantic images}?
			\item How to handle \textbf{all possible formats} (images, multi-layered images, SEM images, 3D tomography...)?
			\item There are so \textbf{many steps where that can go wrong}, or a \textbf{small error slips} into the analysis...
			\item Non-planerized IC exists (non repeated standard cells)! 
			\item And what about \textbf{obfuscation}? 
		\end{itemize}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Human Perspective}		
		\begin{itemize}
			\item Need a \textbf{highly technical level} in several disciplines, this will help for \textbf{error spotting}, choosing a \textbf{zone of interest} and more.
			\item Need to \textbf{understand "silicon"} (how IC are made) and have \textbf{low-level electronic knowledge}.
			\item Have the necessary \\ \textbf{equipment available}.
			\item Be \textbf{persistent} and \textbf{patient}.
			\item \textbf{Practice}.
			\item And \textbf{Have time!}
		\end{itemize}
		
		\vspace{-30mm}
		\hfill\parbox{.65\textwidth}{
			\includegraphics[width=9cm]{res/dect.png}
		}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Importance for Cybersecurity}
		
		How can we \textbf{trust software} if we \textbf{can't trust hardware} (e.g. "specialized" ASIC)?
		
		\vspace{3mm}
		
		\begin{itemize}
			\item Is there any \textbf{vulnerability in the hardware implementation} of an algorithm (e.g. crypto standard with predictable initialization, bad randomness...)?
			\item Is there any \textbf{hardware Trojan} (e.g. placed by the foundry)?
			\item If there is a vulnerability/backdoor, \textbf{patching is impossible}, far \textbf{more impactful} than software vulnerabilities.
		\end{itemize}
		
		\vspace{3mm}
		
		Some examples of vulnerabilities found thanks to silicon RE:
		\begin{itemize}
			\item \textit{Legic Prime}, \textit{NXP Hitag2}, \textit{DECT DSC}, \textit{CryptoRF}, \textit{Atmel CryptoMemory} \& \textit{NXP Mifare Crypto-1} ($\sim$2008, Nohl et al): \textbf{weak (or potentially weak) cryptographic ciphers}.
			\item Undisclosed ones?
		\end{itemize}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
		
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Available Tools \& Products}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{c}
				\parbox{0.4\linewidth}{\small
					Commercial products:
					\begin{itemize}
						\item \href{https://www.texplained.com/about-us/chipjuice-software/}{\textbf{CHIPJUICE}}: 
						Extracting Data from Highly Encrypted ICs.
						\item \textit{Internal tools}: for sure, there is a lot of them.
					\end{itemize}
					
					\vspace{3mm}
					
					Open Source tools:
					\begin{itemize}
						\item \href{https://www.degate.org/}{\textbf{Degate}}
						\item \href{https://github.com/emu-russia/psxrev}{\textbf{psxrev}}: SONY PlayStation PCB/chips reverse engineering.
						\item \href{https://github.com/emu-russia/Deroute}{\textbf{Deroute}}: Tool for untangling wires.
						\item \href{https://github.com/galibert/dietools}{\textbf{dietools}}: Series of tools for die shot reverse-engineering. % from vectorization to netlist
					\end{itemize}
				}
			\end{tabular}
			
			& \begin{tabular}{c}
				\includegraphics[width=7cm]{res/chipjuice.jpg} \\
				\textit{\small(Texplained)}
			\end{tabular}
			
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\section{Degate}
		
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Introduction}
		\textbf{Degate} is a multi-platform software for semi-automatic \textbf{Very-Large-Scale Integration (VLSI) chips reverse engineering} of digital logic in chips.
		
		\vspace{3mm}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{c}
				\parbox{0.4\linewidth}{\small
					\begin{itemize}
						\item $\sim$70k LoC
						\item Supports Mac, Linux \& Windows,
						\item Qt based,
						\item Multi-language support,
						\item Gate definition,
						\item Gate template, via \& wire matching,
						\item Rule checks,
						\item ...
					\end{itemize}
				}
			\end{tabular}
			
			& \begin{tabular}{l}
				\includegraphics[width=7cm]{res/degate1.png}
			\end{tabular}
			
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
		
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{History}
		A long story, with \textbf{technical debt} and \textbf{major IC evolution} (in transistor count), along with a \textbf{small community}.
		
		\vspace{-10mm}
		
		\begin{center}
			\begin{tikzpicture}[very thick, black, rotLabel/.style={above=3pt, anchor= south west, rotate=45}]
				\small
				
				% draw a horizontal line
				\draw (1,0) -- (14,0);
				
				% draw vertical lines
				\foreach \x in {1,2,4,9,10,11,12,14}
				\draw (\x cm,3pt) -- (\x cm,-3pt);
				
				% draw nodes to add events
				\draw (1,0) node[below=3pt] {2007} node[rotLabel] {Martin Schobert \textbf{start developing Degate}};
				\draw (2,0) node[below=3pt] {2008} node[rotLabel] {Famous \textbf{hardware ciphers analysis} w/ Degate};
				\draw (4,0) node[below=3pt] {2010} node[rotLabel] {End of Martin Schobert thesis};
				
				\draw (6.5,0) node[above=0pt] {\footnotesize \textit{(Minimum maintenance)}};
				
				\draw (9,0) node[below=3pt] {2018} node[rotLabel] {\textbf{Forked}, major rewrite};
				\draw (10,0) node[below=3pt] {2019} node[rotLabel] {Vulgarization \textbf{papers}, start working with a lab...};
				\draw (11,0) node[below=3pt] {2020} node[rotLabel] {Pandemic};
				\draw (12,0) node[below=3pt] {2021} node[rotLabel] {Degate \textbf{2.0}};
				\draw (14,0) node[below=3pt] {2023} node[rotLabel] {Degate \textbf{2.1 beta}};
			\end{tikzpicture}
		\end{center}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Usage}
		
		Degate help to reverse \textbf{VLSI chips} by creating an analyzed \textbf{gate library}, doing \textbf{template matching} to find gates instances from this library, \textbf{matching wires \& vias}, \textbf{exporting netlist} and \textbf{navigating really huge images}. \\
		
		\vspace{3mm}
		
		Focus on \textbf{modern ICs} with \textbf{standard cells}, and supports \textbf{any 2D capture/imaging method} (SEM, optical...).
		
		\begin{figure}[!ht]
			\centering
			\resizebox{0.7\textwidth}{!}{%
				\begin{tikzpicture}
					\tikzstyle{every node}=[font=\normalsize]
					
					\draw [, line width=2pt, rounded corners = 93.8] (16.75,21) rectangle (31.5,14.75); % 16.75 -> 14.5
					\node [font=\LARGE] at (24.25,21.5) {\textbf{\underline{Degate 2.0}}}; % 24.25 -> 22.5
					
					\draw [dashed, line width=2pt, rounded corners = 140] (13.5,23) rectangle (34.325,12.75); % 16.75 -> 14.5
					\node [font=\LARGE] at (24.25,13.5) {\textit{\underline{Degate 3.0}}}; % 24.25 -> 22.5
						
					\draw  (10.5,17.75) circle (2.5cm) node [text width=4cm]
					{ \Large
						\centering \textbf{Image chip} \\
						\vspace{3mm}
						\textit{(or SEM scan or 3D tomography)}
					} ;
					\draw  (16.5,17.75) circle (2.5cm) node {\Large \textbf{Analyze Gates}} ;
					\draw  (22.5,17.75) circle (2.5cm) node {\Large \textbf{Trace Wires/Vias}} ;
					\draw  (28.5,17.75) circle (2.5cm) node {\Large \textbf{Generate Netlist}} ;
					\draw [, dashed] (34.5,17.75) circle (2.5cm) node {\Large \textbf{Retrieve Algorithm}} ;
					\draw [->] (13,17.75) -- (14,17.75);
					\draw [->] (19,17.75) -- (20,17.75);
					\draw [->] (25,17.75) -- (26,17.75);
					\draw [->] (31,17.75) -- (32,17.75);
				\end{tikzpicture}
			}%
		\end{figure}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Small Demonstration}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\includegraphics[width=0.8\textwidth]{res/degate_overview.png}
			\end{tabular}
		
			& 
				
			\begin{tabular}{l}
				\hspace{-8mm}
				\parbox{0.225\textwidth}{\footnotesize
					Overview of the chip, for zone of interest selection. \\
					
					A sub-project can then be created on the zone of interest, and specific layers can be added (independent from the rest).
				}
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Small Demonstration}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\includegraphics[width=0.8\textwidth]{res/degate_layers.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\parbox{0.225\textwidth}{\footnotesize
					Each sub-project can contains multiple layers (pre-aligned images). \\
					
					Two project mode: 1. For smaller images, will convert each images in Degate's format (for fast access) and 2. New (WIP, beta) mode for huge images (load only partial tiles in RAM, and doesn't change/import initial file).
				}
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Small Demonstration}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\includegraphics[width=0.8\textwidth]{res/degate_gate.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\parbox{0.225\textwidth}{\footnotesize
					Each gate can be described with VHDL/Verilog, have a list of port (placed on image), a type associated etc.
				}
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Small Demonstration}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\includegraphics[width=0.8\textwidth]{res/degate_instance.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\parbox{0.225\textwidth}{\footnotesize
					Each identified gate (from the gate library) can be matched manually or using template matching algorithms.
				}
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Small Demonstration}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\includegraphics[width=0.8\textwidth]{res/degate_matching.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\parbox{0.225\textwidth}{\footnotesize
					Template matching (will soon be ported to OpenCV) will use gate library to automate gate identification. \\
					
					Currently it uses normalized cross-correlation (with some more steps).
				}
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Small Demonstration}
		
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\includegraphics[width=0.8\textwidth]{res/degate_wires.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\parbox{0.225\textwidth}{\footnotesize
					Wire matching, and specifically port interconnection, is the real challenge (and very error prone). \\
					
					Currently it uses zero crossing edge detection.
				}
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Small Demonstration}
			
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\includegraphics[width=0.8\textwidth]{res/degate_rule.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\parbox{0.225\textwidth}{\footnotesize
					Helpers are available, like rudimentary (but to be improved) rule checking (e.g. for coherency).
				}
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Small Demonstration}
			
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\includegraphics[width=0.8\textwidth]{res/degate_modules.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{l}
				\hspace{-8mm}
				\parbox{0.225\textwidth}{\footnotesize
					Everything can be organized in "module", exported individually (in Verilog/VHDL), etc... "Divide et impera".
				}
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Engineering Challenges}	
		\begin{tabular}{cl}  
			
			\begin{tabular}{l}
				\parbox{0.6\textwidth}{
					\begin{itemize}
						\item Gate template, wires \& vias \textbf{matching}.
						\item Very \textbf{huge images} handling.
						\item \textbf{Error} recovery/acceptance/identification.
						\item Multiple possible \textbf{image format} (e.g. .tiff, .png...) \& \textbf{image source} (e.g. SEM, confocal...).
						\item 10+ years \textbf{old software} (mix of old \& new C++).
						\item \textbf{Collaborative} analysis.
						\item Integrated \textbf{gate analyzer}.
						\item Explicit full \textbf{netlist exporter}.
					\end{itemize}
				}
				
			\end{tabular}
			
			& 
			
			\vspace{8mm}
			\begin{tabular}{cc}
				\includegraphics[width=1.55cm]{res/nand_mifare_transistor.png} &
				\includegraphics[width=1.45cm]{res/nand_legic_transistor.png} \\
				\includegraphics[width=1.48cm]{res/nand_mifare_logic.png} &
				\includegraphics[width=1.45cm]{res/nand_legic_logic.png} \\
				\tiny MIFARE NAND\cite{KarstenNohl2009} &
				\tiny LEGIC NAND\cite{KarstenNohl2009} \\
			\end{tabular}
		\end{tabular}
	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
	
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	\begin{frame}{Research Challenges}
		
		\begin{itemize}
			\item \textbf{3D capture}, imply rethinking Degate (New 3D mode? New software? Really accessible?), and \textbf{new algorithms} (e.g. for matching, tracing and gate identification).
			\item \textbf{Machine learning}/better algorithms for:
				\begin{itemize} 
					\item Auto-\textbf{vectorization} ;
					\item Gate auto \textbf{identification} (from vectorized analysis) ;
					\item Gate auto \textbf{wiring} ;
					\item Auto vias \& wires \textbf{identification}.
				\end{itemize}
			\item Take advantage of certain capture methods such as \textbf{SEM} which makes \textbf{automation easier}.
			\item Making the \textbf{field more accessible} (more automation, new abstractions for analysis, communication...).
			\item Use Degate for \textbf{advanced analysis} and \textbf{published results}.
		\end{itemize}

	\end{frame}
	%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\section{MIFARE Classic Chip Reverse Engineering Case}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{MIFARE Classic Chip \cite{KarstenNohl2009}}
	
	\begin{tabular}{cc}  
		
		\begin{tabular}{c}
			\parbox{0.5\textwidth}{\small
				\vspace{-6mm}
				
				\begin{itemize}
					\item \textbf{RFID card} from NXP launched in 1994.
					\item Used the \textbf{Crypto1 cypher} (until MIFARE Classic EV1, that are using \textbf{Hitag2} cipher).
					\item \textbf{Proprietary encryption} algorithm (stream cipher), security by obscurity.
					\item Cryto1 cipher is only \textbf{implemented in hardware}.
					\item Used (back in 2008) in more than \textbf{3.5 billions cards} (including many building access control systems).
				\end{itemize}
				
				\vspace{3mm}
				
				A \textbf{huge target} with a \textbf{suspicious cypher} and \textbf{security standards}?
			}
		\end{tabular}
		
		& 

		\begin{tabular}{c}
			\includegraphics[width=0.4\textwidth]{res/mifare.png}
		\end{tabular}
	\end{tabular}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Degate's origins \cite{NohlEvans2008}}
	
	\begin{tabular}{cc}  
		
		\begin{tabular}{c}
			\hspace{-7mm}
			\includegraphics[width=0.4\textwidth]{res/mifare_reverse2.png}
		\end{tabular}
		
		& 
		
		\begin{tabular}{c}
			
			\hspace{-10mm}
			\parbox{0.6\textwidth}{\footnotesize
				\begin{itemize}
					\item K. Nohl \& Starbug \textbf{reverse-engineered the Crypto1 cypher} from MIFARE Classic chip in 2007.
					\item Used \textbf{acetone} to dissolve the RFID cards.
					\item Used \textbf{manual polishing} for delayering.
					\item Image a total of \textbf{6 layers}.
					\item Identify zone of interest, \textbf{searching for 48-bit register} \& group of XOR gates.
					\item Used \textbf{standard optical microscope} (500x) \& hugin tool for stitching.
					\item Identified \textbf{around 70 types of gates}.
					\item Used \textbf{home-made scripts} (which became the base of Degate) for \textbf{template matching} to identify all gates.
					\item \textbf{Manually} reconstructed \textbf{connections} between gates.
					\item Made a \textbf{script} to help detecting \textbf{wires} \& \textbf{vias}.
				\end{itemize}
			}
		\end{tabular}
	\end{tabular}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Consequences \cite{NohlEvans2008}}
	\begin{tabular}{cc}  
		\hspace{-10mm}
		\parbox{0.6\textwidth}{\footnotesize
			\begin{itemize}
				\item Using the reverse-engineering results and protocol analysis, authors found \textbf{multiple weakness} in the cipher:
				\begin{itemize}
					\item The cipher is vulnerable to \textbf{brute force} attack, key is too small.
					\item RNG is predictable, it uses a 16-bit LFSR (linear feedback shift register) \textbf{initialized with constant value} and reset at each power-up.
					\item There is \textbf{only one secret key} for each ID that can result to a specific session key, and all shifts are linear.
				\end{itemize}
				\item Meaning that just by \textbf{sniffing interactions} with the card and the reader, we can compute the key and \textbf{retrieve all the data} of the card.
				\item NXP release a retro-compatible \& "hardened" version of the Cipher (Hitag2), which was also weak, MIFARE Classic were \textbf{"discontinued" in 2015}.
			\end{itemize}
		}
		
		& 
		
		\begin{tabular}{c}
			\begin{tabular}{c}
				\hspace{-7mm}
				\includegraphics[width=0.4\textwidth]{res/crypto1.png}
			\end{tabular} \\
			\hspace{-10mm}
			\parbox{0.35\textwidth}{\footnotesize
				\begin{itemize}
					\item Authors \textbf{analyzed other RFID devices} after.
					\item \textbf{Degate was created} from this analysis, used for other RFID devices reverse-engineering and open-sourced in 2008.
				\end{itemize}
			}
		\end{tabular}
	\end{tabular}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\section{Future of Silicon Chip Reverse Engineering}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Future of Silicon Chip RE}
	\begin{itemize}
		\item \textbf{Simpler} and \textbf{cheaper} IC capture (decap \& delayer).
		\item Making the \textbf{field more accessible} (communication, more real-life and useful example/reference analysis...).
		\item \textbf{Shared and open} library of \textbf{chips captures} ($\sim$zeptobar \& siliconpr0n + SiliconZoo).
		\item \textbf{Machine learning} to automate even more analysis steps (\textit{gate identification, wire extract, algorithm retrieving \& analysis})?
	\end{itemize}

	\vspace{3mm}

	There is \textbf{2 EU projects} running around \textbf{ICs reverse-engineering}, but no information on tools, process and analysis \underline{\textbf{sharing}}.
	
	\begin{center}
		\begin{tabular}{cccc}  
			
			\hspace{-13mm}
			
			\begin{tabular}{c}
				\includegraphics[width=0.27\textwidth]{res/google_scholar.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{c}
				\includegraphics[width=0.25\textwidth]{res/old_google_scholar.png}
			\end{tabular}
			
			& 
			
			\hspace{10mm}
			
			\begin{tabular}{c}
				\includegraphics[width=0.1\textwidth]{res/ForRES.png}
			\end{tabular}
			
			& 
			
			\begin{tabular}{c}
				\includegraphics[width=0.1\textwidth]{res/ORSHIN.png}
			\end{tabular}
			
		\end{tabular}
	\end{center}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\section{Bonus}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Which gate is this?}
	% This is a nand, inversed on y axis
	
	\begin{center}
		\begin{tabular}{ccc}
			\includegraphics[width=2.6cm]{res/nand2_transistor_a.png} &
			\includegraphics[width=2.6cm]{res/nand2_logic_a.png} &
			\includegraphics[width=2.6cm]{res/nand2_metal_a.png} \\
			\tiny Transistor layer &
			\tiny Logic layer &
			\tiny Metal layer \\
		\end{tabular}
	\end{center}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\section{References}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}[allowframebreaks]{References}
	\bibliographystyle{plain}
	\bibliography{bibli}
	\nocite{*}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\end{document}

Everything (except Degate’s code, which is GPLv3) is under CC0 license, hence public domain. Feel free to reuse the support, tweak it or present it, even if not crediting me. However, please note that some figures are using a specific, non-CC0, license.

Acknowledgement

I want to thank the original author of Degate, Martin Schobert, and Starbug & Karsten Nohl for their work around silicon chips reverse engineering which inspired me a lot (and were the foundation of Degate).

I also want to thank the community around Degate, contributors and users, for keeping the project alive. And I cannot forget the wider community around the domain of silicon chips reverse engineering, with John McMaster, Ken Shirriff, ZeptoBars or all the others.

And finally, the last releases of Degate were partially sponsored by Anton Kochkov (XVilka), such as the work for this talk. A very huge thank to him.

References

  • Mirko Holler, Manuel Guizar-Sicairos, Esther H. R. Tsai, Roberto Dinapoli, Elisabeth Muller, Oliver Bunk, Jorg Raabe, and Gabriel Aeppli. High-resolution non-destructive three-dimensional imaging of integrated circuits. Nature, 543(7645):402–406, March 2017.
  • Starbug Karsten Nohl. Pacsec silicon conference. 2009.
  • Nils Albartus Ran Ginosara Avi Mendelson Leonid Azriel, Julian Speith and Christof Paar. A survey of algorithmic methods in IC reverse engineering. Cryptology ePrint Archive, Paper 2021/1278, 2021.
  • John McMaster. Siliconpr0n, https://siliconpr0n.org/.
  • Karsten Nohl, David Evans, and Henryk Plotz. Reverse-Engineering a Cryptographic RFID Tag. page 9.
  • Martin Schobert. Gnu software degate. Webpage: http://www.degate.org
  • Berlin Security Research Labs. Siliconzoo, http://siliconzoo.org.
  • Ken Shirriff. Ken shirriff’s blog, https://www.righto.com/.
  • Mikhail Svarichevsky. Zeptobars, https://zeptobars.com/en/.
  • Zonenberg Andrew Yener Bulent. Csci 4974/6974 hardware reverse engineering, 2014.
Degate
Licensed under CC0 (Public Domain), No Rights Reserved.
This blogpost doesn't use any AI-generated text.